1.1 Field of the Invention
Within a processor system consisting of a multitude of functional components encompassing at least one processing unit (PU), also called a CPU, and a clock component the present invention relates to a communication circuitry for connection and data exchange between the clock component and the PU components.
1.2 Description and Disadvantages of Prior Art
A processor system typically consists of various functional components. Depending on the type of requirements and limitations these functional components may be integrated within a single chip or may be dispersed over several separate chips. Due to silicon real estate constraints, many micro-processors do not consist of a single chip, but a chip set. Major components, as a rule, are the basic CPU component, the memory management unit component, a floating point coprocessor component, and a bus adapter component. Mainframe architectures often also includes a separate clock component, a specialized high speed control store component, a memory controller component and a specific service processor component (SP).
The machine cycle is the basic unit of timing in a computer. Within a machine cycle atomic operations, e.g. performing an addition, take place. Instructions are executed within one or several machine cycles. The machine cycle is controlled by an external timing source, an oscillator (usually a crystal) with a constant frequency. Clock logic uses this input to generate various timing signals to control the processor logic at desired timing points within the machine cycle. Existing microprocessor designs implement the clock logic function in one of two different ways:
Either the clock functions are integrated into the individual PU (or CPU component), floating point processor component etc. PA1 Or a separate clock component generates the clock signals for all other components
A typical example of the second approach are IBM/390 processors implementing the IBM/390 mainframe architecture described in the "System/390 Principles of Operation". As those portions of the system that run synchronously may span several chips, the design of the clocking system deserves special attention. If clock signals are distributed over several chips the individual chips may be drastically different with regard to process tolerances. Thus the same clock signal may arrive at the receiving logic spread out in time, referred to as clock skew. A centralized clock component, together with a carefully designed topology for clock signal wiring, significantly reduces clock skew. In addition to the clock generation the clock component performs run control operations, i.e. functions like Start--Stop control, Power on reset recognition, Reset sequence generation for other components, clock checking, and Console key controls.
The clock component generates centrally all the clock signals required by the other components in the system. It requires an external hybrid oscillator and optionally an active delay line. It offers a multitude of different clock signals. The timing of each clock is independently programmable in terms of pulse width, phase, and cycle time, and thus can be adapted to the varying system requirements. The clock signals feed directly the receiving components without any further gating. All clock lines are point to point nets, and clock skews are to be minimized. Clock signals are checked within the clock component.
On power-on recognition the clock component is initialized and clock signal generation starts. The clock signals to be delivered at certain reset and start up points are controlled by the run control.
The clock component is the master of the component set for the reset function, which typically include "Power on Reset", "Reset for IML", "System Reset", "Check Reset", "Start after Reset" and so forth.
The clock component typically provides further external hardware interfaces, implemented in IBM/390 systems as a five-line support bus of two bit lines (in/out) and three control lines, to cause the clock component to execute functions mentioned above. For instance an auxiliary processor, the so-called service processor (SP), may exploit this external interface of the clock component for an overall control of the processor.
Current state of the art technology, as realized for example within the current IBM/390 systems, uses multiple signal pins and corresponding signal lines between the clock component and the PU components. Within a /390 system there are 5 signal lines connecting the clock and a PU component associated with the following meaning:
1. Micro Instruction Step PA0 2. Micro Instruction Address Compare PA0 3. Soft Stopped Sate PA0 4. Wait State PA0 5. Malfunction Alert
The drawbacks of the above approach of connecting and communicating become evident and striking once an attempt is made to build a system with not only a single PU component. The disadvantages with respect to the state of the art approach, which already are present also in the case of a single PU component, increase with the number of PU components and may result in the infeasibility of building a multi-processor system with a larger number of PUs.
Due to the large number of signal lines connecting the clock component and a multitude of PU components the state of the art approach hinders to realize multi-processor systems.
To demonstrate the urgent need to optimize the communication technology between the service processor (SP) and a PU in terms of the required number of signal pins one has to shed further light on the current state of the art approach. The current implementation within a /390 system shows 5 signal pins and signal lines connecting the clock and a PU component associated with the meanings mentioned above. Assume for the moment a typical multi-processor system of current stat of the art technology. It is assembled of 2 so-called Multi-Chip-Modules (MCM) each comprising 6 PU components. The signals 1 to 4 of above list are individual to each PU and thus contribute 24 signals to a MCM. The 5-th signal is a multidrop net that is received by each PU component. Due to driving limitations this 5-th signal does not account for 6 but for 12 signals per MCM. All in all this state of the art example shows that 36 signals are necessary for the communication between the clock and an MCM. The situation on the clock component is even worse; as it communicates to 2 MCMs all in all the immense number of 72 signals are required. Further extensions of the number of PUs are significantly hindered by the current clock-to-PU communication technology. Testing of these huge number of lines causes further sever problems.
The large number of signal lines between PU components and the clock component would have to be connected to the clock chip at the boundary of the 2-dimensional chip. Due to spatial requirements for the individual signal lines the size of a component to a large extend is determined by the number of input/output signals; the clock component would have to be increased significantly just to be able to direct the signal lines to the clock chip's boundary. This would result in a clock component much larger in size than required for the actual clock component circuitry. Thus as a consequence unused and therefore wasted chip size would be a further outcome, not to talk about the difficulties of arranging and distributing the huge number of signal lines between clock and PU components within the micro processor system.
A linear increasing of the number of signal pins on the clock component with the number of PU components in addition drastically impede the manufacturing process and at the same time increasing the requirements for the manufacturing process itself.
The state of the art approach offers no concept to validate whether the transmitted data has been correctly received by the PU component. Extended error detection and error correction with respect to information exchange between clock and a PU component is not supported, being a central issue in a multiple PU system as with increasing number of components the probability for error situations is increased.
Furthermore the large number of signal lines in a multiple PU system exploiting the state of the art approach would significantly jeopardize noise immunity on the clock lines without any chance and support to detect and localize the error.
1.3 Objective of the Invention
The invention, related to a processor system, is based on the objective to provide a new kind of clocking concept and circuitries for communication between the clock and the PU components within a multi-processor system. The invention should help to remove the obstacles in building processor systems with a larger number of PU components.